This invention relates to a semiconductor device and method of fabricating the same, and more particularly to a semiconductor device having fine and low-resistance current paths flowing in element regions of a bipolar integrated circuit element, an FET integrated circuit element or the like and method of fabricating the same.
Recently, in the field of semiconductor devices, in particular, semiconductor integrated circuit devices, fine processing technology has been introduced to cope with the higher density, lower power consumption, and higher speed of these devices. To realize high speed in a bipolar NPN transistor, for example, it is necessary to lower the parasitic resistance of each junction, aside from decreasing the parasitic capacity of an element by using shallow and fine junctions or decreasing the element isolation capacity by using dielectric isolation. With CMOS or other transistors, as in bipolar elements, it is required to decrease the parasitic resistance among junctions in order to prevent the latch-up phenomenon, as well as to form fine junctions and improve the element isolation. For example, in the bottom of an n-type low impurity concentration well of a CMOS, an n-type element region of high impurity concentration is formed by high energy ion-implantation, or a buried layer region of high impurity concentration is formed in the bottom of a well when developing a substrate by epitaxial growth, in attempts to decrease the parasitic resistance among junctions.
For this reduction of resistance, in conventional semiconductor devices, a buried low resistance semiconductor region having high impurity concentration was formed beneath the insular element region. As the method of taking out an electric current from this low resistance semiconductor region into the surface of semiconductor, the semiconductor region having a high concentration of impurity deeply diffused from the semiconductor surface is connected to the buried low resistance semiconductor region, and this semiconductor region formed by deep diffusion is utilized as a current path. For example, as mentioned in Symposium on VLSI Technology Digest of Technical Papers, pp. 42-43, a groove to isolate the NPN transistor region in an insular form is formed in a width of about 2.mu. and a depth of about 5.mu., and this groove is filled up with polycrystalline silicon to flatten the surface. Beneath the n-type epitaxial layer which becomes part of the insular element region, a low resistance buried semiconductor region (sub-collector) having an n-type high concentration impurity is formed. Contacting with this sub-collector, an n-type deep low resistance semiconductor region is formed, and the collector electrode is connected in this region. The two low resistance regions with which the sub-collector region and deep low resistance region contact serve as low resistance current paths of the collector current flowing between the emitter electrode and collector electrode. The deep low resistance semiconductor region is formed by diffusion from the surface of epitaxial semiconductor layer, and has a depth of about 1 to 2.mu.. The following points may be picked up as the problems, in both structure and manufacturing process, of this low resistance semiconductor region.
(1) When forming a low resistance region by the diffusion method, the lateral diffusion (yi) spreads about 70% of the depth in the longitudinal direction (xj), and the width of the low resistance region substantially increases, and a large dimensional change occurs with respect to the diffusion opening of the mask design, and this lateral diffusion is contrary to the micronization of elements.
(2) When forming a low resistance region by the diffusion method, since high temperature is required for a long period for diffusion, this region cannot be formed after shallow diffusion for forming a base region or the like. Besides, since the impurity profile in the sub-collector region is easily broken, it is difficult to obtain a steep impurity profile suited to high speed. That is, in the low temperature manufacturing process for forming a shallow junction for high speed, it is not preferable to form a deep region with low resistance.
(3) Due to the foregoing reason (1), unless the lateral diffusion is inhibited, the distance to the base region becomes shorter, and the electric junction tolerance tends to deteriorate.
(4) When the n-type impurity concentration is high on the surface of the low resistance region, stress is likely to occur in single crystals of the semiconductor layer, which may lead to crystal defects.